Huawei Ascend 950DT will debut in August this year, and ahead of its official unveiling, the die-chip design of this semiconductor has surfaced online. A new leak reveals the internal components of the upcoming Ascend processor in advance.
X blogger @zephyr_z9 mentioned the die-chip design details of the Huawei Ascend 950DT. It mentioned that the upcoming processor has only four HiZQ die stacks compared to the Ascend 950PR, which has a total of 10 dies.
He shared an image showing that the standard Ascend 950 chipset has a multi-die packaged design. It integrates 2 AI dies and 10 stacked dies. On the flip side, the Ascend 950PR has a total of 8 dies stacked with each other.
But the all-new Ascend 950DT will feature four high-speed on-chip memory modules. These dies and other components are directly connected through high-speed D2D Clink and Memory Interface.
Thus, the entire chiplet design forms a Unified Memory Access (UMB) system. Also, each HiZQ stack has an aggregate bandwidth of 1 TB/s (between HBM 3 and HBM3E).
(Image Credits: X)
D2D Clink or Die-to-Die Clink refers to a proprietary, high-performance PHY (physical layer interface) technology used for chiplet communication inside modern computing architectures like high-performance AI semiconductors.
It further enables multiple smaller, specialized silicon dies like AI processing units and memory to stack together and communicate seamlessly while functioning as a single, highly unified chip.
Simply put, despite fewer dies, the Ascend 950DT could offer a significant boost in AI performance and efficiency over the previous versions. Other details are still unclear. Though we likely have to wait for one more month to know the official parameters.
