TSMC is reportedly working on a cutting-edge chip packaging technology called CoPoS, which may debut by 2028. Analyst Ming-Chi Kuo has given an idea of what new changes the company is bringing to its semiconductors in the next two years.
Ming has revealed “key takeaways” regarding the next-generation TSMC chip packaging technology – CoPoS, probably coming in 2028. The new solution will not only relieve the company in terms of spendings but also boost the chip performance.
CoPoS – TSMC’s all-new Chip-on-Panel-on-Structure technology will usually focus on massive ultra-large AI and High-Performance Computing (HPS) processors.
According to Ming, CoPoS may enter tthe mass production phase in the second half of 2028. It will be first used in NVIDIA’s Feynman AI chipset and can improve the cost-effectiveness of ultra-large packages over 9.5x reticle-size.
TSMC CoPoS uses a glass material that serves two major purposes. The first is temporary glass carriers with 310 x 310mm dimensions. And the second is as a final substrate with a three-layer sandwich structure.
The analyst further cleared certain misconceptions regarding the new chip packaging technology. He mentioned that CoPoS does not use glass as an interposer. Rather, the chip-side RDL handles interconnect role, TGV/Cu links and ABF build-up layers in the glass-core substrate stack.
Both glass and ABF coexist and the chips are attached to the ABF build-up sirafce of the glass core substrate.5. The new tech will likely extend TSMC’s leadership in advanced packaging, giving that advantage visibility through around 2032.
(Image Credits: TSMC)
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