Huawei announced to base its 2026 Kirin chip on the Tau Law, and the company is now revealing more details of this tech breakthrough with a paper version 2. The OEM has now dropped the “time scaling theory for multi-layer electronic systems”.
Tingbo He, the head of Huawei Semiconductor Unit, has released the Tau Chip Law version 2 paper. It details the new chip innovation and relevant engineering information.
The chief executive revealed the paper version 1 in May this year, introducing the new Tau Law and LogicFolding design architecture for future Huawei semiconductors.
Now the paper version 2 shows details regarding engineering implementation, actual measurement data, and the product evolution roadmap for the main framework.
(Image Credits: Huawei)
It also sheds light on how the company will further improve the post-Moore’s Law scaling theory part by using the time constant τ as the fundamental unit.
Speaking of the paper, it has some diagrams that define the principles of the Tau Law. It covers core technologies like the Tau-layered spatiotemporal model, LogicFolding design architecture, interface cross-section, Unified Bus frame, and Hi-ONE.
The paper explains the core concept of “gear ratio” in LogicFolding. When the hybrid bonding pitch approaches the top-layer metal wiring dimensions, the 3D design jumps to cell-level constant optimization instead of relying on the macro-block level.
As a result, it allows optical logic partitioning to overcome the limitations of traditional 3D stacking that used to layer only by functional blocks. A chart in the paper reveals the voltage, frequency, power consumption, area, and power density of Kirin 2026 chips.
Unlike Moore’s Law, Tau Law is based on adopting time rather than transistor area as the primary metric of progress. Meanwhile, LogicFolding partitions digital, analog, and memory circuits across stacked tiers with a 55% step-wise boost in transistor density. Besides, it provides a 41% increase in power efficiency at a fixed device node.
(Image Credits: Huawei)
